Power Management Unit ----PMU
时间：2010-08-30 来源：xxha000721
18.4 power status
1. core-level power status
a. active status
b. internal idle status or idle status
c. power down status
2. chip-level power status
a. sleep state with VCXO on
b. sleep state with VCXO off
c. power off
18.8 power management unit 18.8.1 Main PMU
Responsible for chip-level power management .
Once the AP Subsystem PMU and CPMU enter the lowest power state, the Main PMU takes control of the chip-level low power states.
18.8.1.4 power states controlled by Main PMU
1. chip-level idle state exit. each of the following can cause this happen.
a. application subsystem clock resume
b. FEIC(MSA) wake up request
c. baseband clock resume.
2. chip-level sleep state exit.
a.
3. chip-level idle state entry.
a. MSA subsystem clock shut down
b. application subsystem clock shut down
c. AXI domain clock shutdown
d. AXI domain and APB domain clock shutdown
4. bus domain shutdown
the bus shutdown is stopping the clocks of AXI fabrics and DDR.
5. APB idle state entry and exit.
6. chip-level sleep state entry.
7. baseband logic clock control.
18.8.1.5 PMU sleep wakeup decoder
18.8.1.6 resets
18.8.2 application subsystem PMU
1. modem ARM(*seagull) core processor clocking and low power mode state machine.
2. PJ1 core processor clocking and low power mode state machine.
3. AXI fabrics and DDR clocking and low power mode state machine.
18.8.2.2 clock and power control
1. core power down
2. core idle
3. application subsystem idle
4. application subsystem sleep
---core power state machine
entering the powerdown mode
exiting from the powerdown mode
---core powerdown
18.8.2.3 wakeup scienarios
1. wakeup from core powerdown
2. wake from core idle
3. wake from application idle
4. wake from application sleep
18.8.2.4 software and hardware sequence for application subsystem PMU low power states
---core idle entry and exit
---application idle entry and exit
---application sleep entry and exit
18.8.3 CCU and CPMU
CCU --- control the generation and gating of the MSA subsystem clocks.
CPMU --- control the MSA subsystem power states.
18.8.3.2 power states controled by CCU and CPMU
1. MSA core idle
2. MSA subsystem idle
3. MSA subsystem sleep
18.8.4 MSA PMU
18.8.4.1 power up and idle states
1. active
2. core idle and subsystem active.
3. subsystem idle .
b. internal idle status or idle status
c. power down status
2. chip-level power status
a. sleep state with VCXO on
b. sleep state with VCXO off
c. power off
18.8 power management unit 18.8.1 Main PMU
Responsible for chip-level power management .
Once the AP Subsystem PMU and CPMU enter the lowest power state, the Main PMU takes control of the chip-level low power states.
18.8.1.4 power states controlled by Main PMU
1. chip-level idle state exit. each of the following can cause this happen.
a. application subsystem clock resume
b. FEIC(MSA) wake up request
c. baseband clock resume.
2. chip-level sleep state exit.
a.
3. chip-level idle state entry.
a. MSA subsystem clock shut down
b. application subsystem clock shut down
c. AXI domain clock shutdown
d. AXI domain and APB domain clock shutdown
4. bus domain shutdown
the bus shutdown is stopping the clocks of AXI fabrics and DDR.
5. APB idle state entry and exit.
6. chip-level sleep state entry.
7. baseband logic clock control.
18.8.1.5 PMU sleep wakeup decoder
18.8.1.6 resets
18.8.2 application subsystem PMU
1. modem ARM(*seagull) core processor clocking and low power mode state machine.
2. PJ1 core processor clocking and low power mode state machine.
3. AXI fabrics and DDR clocking and low power mode state machine.
18.8.2.2 clock and power control
1. core power down
2. core idle
3. application subsystem idle
4. application subsystem sleep
---core power state machine
entering the powerdown mode
exiting from the powerdown mode
---core powerdown
18.8.2.3 wakeup scienarios
1. wakeup from core powerdown
2. wake from core idle
3. wake from application idle
4. wake from application sleep
18.8.2.4 software and hardware sequence for application subsystem PMU low power states
---core idle entry and exit
---application idle entry and exit
---application sleep entry and exit
18.8.3 CCU and CPMU
CCU --- control the generation and gating of the MSA subsystem clocks.
CPMU --- control the MSA subsystem power states.
18.8.3.2 power states controled by CCU and CPMU
1. MSA core idle
2. MSA subsystem idle
3. MSA subsystem sleep
18.8.4 MSA PMU
18.8.4.1 power up and idle states
1. active
2. core idle and subsystem active.
3. subsystem idle .
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