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关于mx27 DMA 驱动
我们先来看一下涉及的数据结构：
/*! This defines the DMA channel parameters */
typedef struct mxc_dma_channel {
unsigned int active:1; /*!< When there has a active tranfer, it is set to 1 */
unsigned int lock; /*!< Defines the channel is allocated or not */
int curr_buf; /*!< Current buffer */
mxc_dma_mode_t mode; /*!< Read or Write */
unsigned int channel; /*!< Channel info */
unsigned int dynamic:1; /*!< Channel not statically allocated when 1 */
char *dev_name; /*!< Device name */
void *private; /*!< Private structure for platform */
mxc_dma_callback_t cb_fn; /*!< The callback function */
void *cb_args; /*!< The argument of callback function */
} mxc_dma_channel_t;
一看就知道这个是描述DMA通道的，这里的active和dynamic还用了位域定义，有这个必要吗？然后在dma_mx2.c的最前面定义了这么一个静态数组：
static mxc_dma_channel_t g_dma_channels[MAX_DMA_CHANNELS];
/*!
* Structure of dma buffer descriptor
*/
typedef struct {
unsigned long state; /*!< dma bd state */
int mode; /*!< the dma mode of this bd */
unsigned long count; /*!< the length of the dma transfer */
unsigned long src_addr; /*!< the source address of the dma transfer */
unsigned long dst_addr; /*!< the destination address of the dma transfer */
} mx2_dma_bd_t;
/*!
* This structure containing the private information for MX2
*/
typedef struct mx2_dma_priv_s {
unsigned int dma_chaining:1; /* 1: using headware dma chaining feature */
unsigned int ren:1; /* 1: dma start besed on request signal */
unsigned long trans_bytes; /* To store the transfered data bytes in this transfer */
mx2_dma_info_t *dma_info; /* To store the pointer for dma parameter for reading and wirting */
int bd_rd; /* the read index of bd ring */
int bd_wr; /* the write index of bd ring */
atomic_t bd_used; /* the valid bd number in bd ring */
mx2_dma_bd_t *bd_ring; /* the pointer of bd ring */
unsigned long dma_base; /* register base address of this channel */
int dma_irq; /* irq number of this channel */
} mx2_dma_priv_t;
这个BD和FEC里的BD可是两个东西，这里的BD只是纯软件的定义，不像FEC里的BD有相应的硬件寄存器。这里也用了两个位域dma_chaining和ren，接下来dma_mx2.c中有定义：
static mx2_dma_priv_t g_dma_privates[MXC_DMA_CHANNELS];
static mx2_dma_bd_t g_dma_bd_table[MXC_DMA_CHANNELS][MAX_BD_SIZE];
其中MXC_DMA_CHANNELS为16，MAX_BD_SIZE为64
下面来看一下这个数据结构：
/*! This defines the list of device ID's for DMA */
typedef enum mxc_dma_device {
MXC_DMA_UART1_RX,
MXC_DMA_UART1_TX,
MXC_DMA_UART2_RX,
MXC_DMA_UART2_TX,
MXC_DMA_UART3_RX,
MXC_DMA_UART3_TX,
MXC_DMA_UART4_RX,
MXC_DMA_UART4_TX,
MXC_DMA_UART5_RX,
MXC_DMA_UART5_TX,
MXC_DMA_UART6_RX,
MXC_DMA_UART6_TX,
MXC_DMA_MMC1_WIDTH_1,
MXC_DMA_MMC1_WIDTH_4,
MXC_DMA_MMC2_WIDTH_1,
MXC_DMA_MMC2_WIDTH_4,
MXC_DMA_SSI1_8BIT_RX0,
MXC_DMA_SSI1_8BIT_TX0,
MXC_DMA_SSI1_16BIT_RX0,
MXC_DMA_SSI1_16BIT_TX0,
MXC_DMA_SSI1_24BIT_RX0,
MXC_DMA_SSI1_24BIT_TX0,
MXC_DMA_SSI1_8BIT_RX1,
MXC_DMA_SSI1_8BIT_TX1,
MXC_DMA_SSI1_16BIT_RX1,
MXC_DMA_SSI1_16BIT_TX1,
MXC_DMA_SSI1_24BIT_RX1,
MXC_DMA_SSI1_24BIT_TX1,
MXC_DMA_SSI2_8BIT_RX0,
MXC_DMA_SSI2_8BIT_TX0,
MXC_DMA_SSI2_16BIT_RX0,
MXC_DMA_SSI2_16BIT_TX0,
MXC_DMA_SSI2_24BIT_RX0,
MXC_DMA_SSI2_24BIT_TX0,
MXC_DMA_SSI2_8BIT_RX1,
MXC_DMA_SSI2_8BIT_TX1,
MXC_DMA_SSI2_16BIT_RX1,
MXC_DMA_SSI2_16BIT_TX1,
MXC_DMA_SSI2_24BIT_RX1,
MXC_DMA_SSI2_24BIT_TX1,
MXC_DMA_FIR_RX,
MXC_DMA_FIR_TX,
MXC_DMA_CSPI1_RX,
MXC_DMA_CSPI1_TX,
MXC_DMA_CSPI2_RX,
MXC_DMA_CSPI2_TX,
MXC_DMA_CSPI3_RX,
MXC_DMA_CSPI3_TX,
MXC_DMA_ATA_RX,
MXC_DMA_ATA_TX,
MXC_DMA_MEMORY,
MXC_DMA_DSP_PACKET_DATA0_RD,
MXC_DMA_DSP_PACKET_DATA0_WR,
MXC_DMA_DSP_PACKET_DATA1_RD,
MXC_DMA_DSP_PACKET_DATA1_WR,
MXC_DMA_DSP_LOG0_CHNL,
MXC_DMA_DSP_LOG1_CHNL,
MXC_DMA_DSP_LOG2_CHNL,
MXC_DMA_DSP_LOG3_CHNL,
MXC_DMA_CSI_RX,
MXC_DMA_TEST_RAM2D2RAM,
MXC_DMA_TEST_RAM2RAM2D,
MXC_DMA_TEST_RAM2D2RAM2D,
MXC_DMA_TEST_RAM2RAM,
MXC_DMA_TEST_HW_CHAINING,
MXC_DMA_TEST_SW_CHAINING
} mxc_dma_device_t;
这里枚举了MX27系统中的预先定义好的ID，而与这些ID相对的还有它的属性：
static dma_info_entry_t active_dma_info[] = {
{MXC_DMA_TEST_RAM2RAM, &ram2ram_dma_info},
{MXC_DMA_TEST_RAM2D2RAM2D, &ram2d2ram2d_dma_info},
{MXC_DMA_TEST_RAM2RAM2D, &ram2ram2d_dma_info},
{MXC_DMA_TEST_RAM2D2RAM, &ram2d2ram_dma_info},
{MXC_DMA_TEST_HW_CHAINING, &hw_chaining_dma_info},
{MXC_DMA_TEST_SW_CHAINING, &sw_chaining_dma_info},
{MXC_DMA_ATA_RX, &ata_rx_dma_info},
{MXC_DMA_ATA_TX,
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