将华邦w90p710移植到skyeye上面---仅供参考
时间：2006-11-10 来源：shenghuo456
/***********************************************************************/
一点说明：以下代码模拟了w90p710的硬件时钟、中断、串口三个方面，由于比较仓促，所以代码未
进行优化，个人认为要加入一个board最重要的是对芯片非常了解。
我的移植步骤：
1、把.h和相应的.c放到相应的目录，修改makefile，加进所有关于W90P710的信息
2、修改skyeye.conf，对ram和rom的设置请按华邦bsp的menuconfig配置来设置。
3、开始写代码了
首先模拟时钟中断，代码见红色标号1处，采用timer0，isr方式中断，w90p710的isr中断方式是把中断屏蔽位和中断标志位同时有效的中断保存在isr寄存器中，然后在do_irq里面判断优先级，而iper中断方式则是把中断屏蔽位和中断标志位同时有效，且优先级最高的中断号放在iper里面。需要好好的写中断控制器的模拟代码，不然整个系统很难起来。
4.写模拟串口操作，只要读懂芯片的datasheet，用软件去模拟每一个寄存器的基本功能，是很容易的，由于我run起来跑的挺慢的，且我这里开发板多的是，我最终还是放弃了进一步的模拟工作。部分主要模拟代码如下：
/***********************************************************************/
ARMword W90P710_io_read_word (ARMul_State * state, ARMword addr);
void W90P710_io_write_word (ARMul_State * state, ARMword addr, ARMword data); /* W90P710 Internal IO Registers
* */
typedef struct W90P710_io
{
/*********************************/ /*System Manager control */
ARMword pdid;
ARMword arbcon;
ARMword pllcon;
ARMword clksel; /*Interrupt Controller Registers */
ARMword aic_scr[31];
ARMword aic_irsr;
ARMword aic_iasr;
ARMword aic_isr;
ARMword aic_iper;
ARMword aic_isnr;
ARMword aic_imr;
ARMword aic_oisr;
ARMword aic_mecr;
ARMword aic_mdcr;
ARMword aic_sscr;
ARMword aic_sccr;
ARMword aic_eoscr;
ARMword aic_test;
ARMword aic_fiq;
ARMword aic_irq;
/*UART Registers */
ARMword com_tx;
ARMword com_rx;
ARMword com_dll;
ARMword com_dlm;
ARMword com_ier;
ARMword com_iir;
ARMword com_fcr;
ARMword com_lcr;
ARMword com_mcr;
ARMword com_lsr;
ARMword com_msr;
ARMword com_tor; /*Timers Registers */
ARMword tcr0;
ARMword tcr1;
ARMword ticr0;
ARMword ticr1;
int tdr0;
int tdr1;
ARMword tisr;
ARMword wtcr;
/*cache register*/
ARMword cahcnf;
ARMword cahcon;
ARMword cahadr; } W90P710_io_t;
static W90P710_io_t W90P710_io;
#define io W90P710_io
static int ENABLE_TIMER0=0;
static int ENABLE_TIMER1=0;
static unsigned char mac_buf[4096]; int JUDGE_ENABLE_TIMER(int timer)
{
int IE=0,CEN=0,nDBGACK_EN=0;
if(timer==0){
if (io.tcr0&0x20000000) {IE=1;io.aic_isr|=1<<(INT_TIMER0);}
if (io.tcr0&0x40000000) CEN=1;
if (io.tcr0&0x80000000) nDBGACK_EN=1;
if (IE&CEN&nDBGACK_EN) {
io.tdr0=io.ticr0;
return ENABLE_TIMER0=1;
}
}
}
static void
W90P710_update_int (ARMul_State * state)
{
ARMword requests = io.aic_iasr & io.aic_mecr;
/*DEBUG MY FUN*/
debug_zswan_register_key(requests ,"W90P710_update_int-requests & io.aic_irq",0);
/*because i have use the fiq,i delete it*/
state->NirqSig = (requests) ? LOW : HIGH;
//if(requests)
// state->NirqSig =0;
//else
// state->NirqSig =1;
}
static void
W90P710_set_interrupt (unsigned int irq)
{
/*DEBUG MY FUN*/
debug_zswan_register_key(io.aic_iasr,"W90P710_set_interrupt-io.aic_iasr",0);
io.aic_iasr |= (1 << irq);
}
static void
Set_uart_tx_rx_interrupt (int rxtx,ARMul_State * state)
{
int Receiver=1 ,Transmitter=0;
//io.aic_iasr |= (1<<9);
//io.com_iir &= ~0x01;
//Receiver |= ~0x01;
if(rxtx==Receiver){
printf("---Start Receiver interrupt call cpu to get the com_rx---\n");
io.com_iir =UART_IIR_DR;
io.com_lsr |=UART_LSR_RFDR;
}
if(rxtx==Transmitter){
printf("---Start Transmitter interrupt call cpu to put the com_tx---\n");
io.com_iir =UART_IIR_THRE;
io.com_lsr |=UART_LSR_THRE;
}
W90P710_set_interrupt(INT_UARTRX0);
W90P710_set_AICISR(INT_UARTRX0);
W90P710_update_int (state);
io.aic_iasr &= ~(1<<9);
}
void
W90P710_set_AICISR (unsigned int irq)
{
io.aic_iasr |= (1 << irq);
io.aic_mecr |= (1 << irq);
io.aic_isr|=io.aic_iasr&io.aic_mecr;
/*DEBUG MY FUN*/
debug_zswan_register_key(io.aic_iasr,"W90P710_set_AICISR-io.io.aic_isr",0);
}
static int
W90P710_pending_intr (u32 interrupt)
{
return ((io.aic_iasr & (1 << interrupt)));
}
static void
W90P710_update_intr (void *mach)
{
struct machine_config *mc = (struct machine_config *) mach;
ARMul_State *state = (ARMul_State *) mc->state;
W90P710_update_int (state);
}
static void
W90P710_io_reset (ARMul_State * state)
{
/*DEBUG MY FUN*/
debug_zswan_register_key(0,"W90P710 RESET FUNC",0);
/*INIT MY IO REGISTER*/
memset (&W90P710_io, 0, sizeof (W90P710_io));
io.aic_isr = 0x0;
io.aic_mecr=0x0;
io.aic_isr=0x0;
io.aic_iper=0x0;
io.com_iir=0x81818181;
io.com_lsr=0x60606060;
//io.com_ier=0x02|0x01;
}; /*W90P710 io_do_cycle*/
void
W90P710_io_do_cycle (ARMul_State * state)
{
unsigned int t;
fd_set rfds;
struct timeval tv;
int maxfd;
/*Timer */
if (ENABLE_TIMER0) {=====〉1
EBUG MY FUN*/
debug_zswan_register_key(io.tdr0,"io.tdr0--",0);
/*SET INIT DATA*/
io.tdr0--;
if (io.tdr0 < 0) {
/*DEBUG MY FUN*/
debug_zswan_register_key(io.tdr0,"io.tdr0<0",0);
/*RELOAD THE DATA*/
//io.tisr=0x1;
io.tdr0 = io.ticr0;
/*SET UCLINUX INTERRUPPT*/
W90P710_set_interrupt (INT_TIMER0);
/*SET AIC TO UC ENTRY-ARMV.S*/
W90P710_set_AICISR(INT_TIMER0);
W90P710_update_int (state); return;
}
}
/*UART*/
FD_SET (skyeye_config.uart.fd_in, &rfds);
maxfd = skyeye_config.uart.fd_in;
tv.tv_sec = 0;
tv.tv_usec = 0;
if (select (maxfd + 1, &rfds, NULL, NULL, &tv) > 0) {
if (FD_ISSET (skyeye_config.uart.fd_in, &rfds)) {
unsigned char buf;
int n;
n = read (skyeye_config.uart.fd_in, &buf, 1);
if (n > 0) {
if (buf == 1) buf = 3;
io.com_rx = (int) buf;
Set_uart_tx_rx_interrupt(1,state);
//io.aic_iasr &= ~(1<<9);
}
}
}
W90P710_update_int (state);
}
/* IO Read Routine */
ARMword
W90P710_io_read_byte (ARMul_State * state, ARMword addr)
{
debug_zswan("W90P710_io_read_byte");
//printf("SKYEYE: W90P710_io_read_byte error\n");
W90P710_io_read_word (state, addr);
}
ARMword
W90P710_io_read_halfword (ARMul_State * state, ARMword addr)
{
debug_zswan("W90P710_io_read_halfword");
//printf("SKYEYE: W90P710_io_read_halfword error\n");
W90P710_io_read_word (state, addr);
}
ARMword
W90P710_io_read_word (ARMul_State * state, ARMword addr)
{
debug_zswan("W90P710_io_read_word");
ARMword data = -1;
switch (addr) {
/*System Manager control */
case PDID:
data=io.pdid;
break;
case ARBCON:
data=io.arbcon;
break;
case PLLCON:
data=io.pllcon;
break;
case CLKSEL:
data=io.clksel;
break;
/*Interrupt source Registers */
case AIC_SCR1:
data=io.aic_scr[0];
break;
case AIC_SCR2:
data=io.aic_scr[1];
break;
case AIC_SCR3:
data=io.aic_scr[2];
break;
case AIC_SCR4:
data=io.aic_scr[3];
break;
case AIC_SCR5:
data=io.aic_scr[4];
break;
case AIC_SCR6:
data=io.aic_scr[5];
break;
case AIC_SCR7:
data=io.aic_scr[6];
break;
case AIC_SCR8:
data=io.aic_scr[7];
break;
case AIC_SCR9:
data=io.aic_scr[8];
break;
case AIC_SCR10:
data=io.aic_scr[9];
break;
case AIC_SCR11:
data=io.aic_scr[10];
break;
case AIC_SCR12:
data=io.aic_scr[11];
break;
case AIC_SCR13:
data=io.aic_scr[12];
break;
case AIC_SCR14:
data=io.aic_scr[13];
break;
case AIC_SCR15:
data=io.aic_scr[14];
break;
case AIC_SCR16:
data=io.aic_scr[15];
break;
case AIC_SCR17:
data=io.aic_scr[16];
break;
case AIC_SCR18:
data=io.aic_scr[17];
break;
case AIC_SCR19:
data=io.aic_scr[18];
break;
case AIC_SCR20:
data=io.aic_scr[19];
break;
case AIC_SCR21:
data=io.aic_scr[20];
break;
case AIC_SCR22:
data=io.aic_scr[21];
break;
case AIC_SCR23:
data=io.aic_scr[22];
break;
case AIC_SCR24:
data=io.aic_scr[23];
break;
case AIC_SCR25:
data=io.aic_scr[24];
break;
case AIC_SCR26:
data=io.aic_scr[25];
break;
case AIC_SCR27:
data=io.aic_scr[26];
break;
case AIC_SCR28:
data=io.aic_scr[27];
break;
case AIC_SCR29:
data=io.aic_scr[28];
break;
case AIC_SCR30:
data=io.aic_scr[29];
break;
case AIC_SCR31:
data=io.aic_scr[30];
break;
/*Interrupt Controller Registers */
case AIC_IRSR:
data=io.aic_irsr ;
break;
case AIC_IASR:
data=io.aic_iasr ;
break;
case AIC_ISR:
data=io.aic_isr;
debug_zswan_register_key(io.aic_isr,"io.aic_isr",0); break;
case AIC_IPER:
{
int j,k,find[31],max[31];
int max_level,max_irq,l=0;
for(j=0;j<32;j++){
if(((io.aic_iasr) & (1 << j))&((io.aic_mecr & (1 << j)))){
find[l++]=j;
max[l]=io.aic_scr[(find[l--]-1)]&0x07;
l++;
max[l]=7;
continue;
}
}
if(l==0) data=0;
else{
max_level=max[l];
for(j=l;j>0;j--){
if (max[j-1]<=max_level){
max_level=max[j-1];
max_irq=find[j-1];
}
}
}
data=(max_irq<<2);
debug_zswan_register(data,"io.AIC_IPER");
io.aic_isnr=max_irq;
//if(max_level==0) state->NfiqSig =1 ;
//else state->NirqSig =1 ;
}
break;
case AIC_ISNR:
data=io.aic_isnr;
break;
case AIC_IMR:
data=io.aic_imr;
break;
case AIC_OISR:
data=io.aic_oisr;
break;
case AIC_MECR:
data=io.aic_mecr;
break;
case AIC_MDCR:
data=io.aic_mdcr;
break;
case AIC_SSCR:
data=io.aic_sscr;
break;
case AIC_EOSCR:
data=io.aic_eoscr;
break;
case AIC_TEST:
data=io.aic_test;
break;
/*UART Registers */
case COM_RX:
//data=io.com_tx;
data=io.com_rx;
//data=io.com_dll;
io.com_lsr &= ~UART_LSR_RFDR;
io.com_iir &= ~UART_IIR_DR;
io.aic_iasr &= ~(1<<9);
debug_zswan_register_key(io.com_rx,"start to get com_rx",0);
break;
case COM_IER:
//data=io.com_dlm;//ok?
data=io.com_ier;
break;
case COM_IIR:
//data=io.com_fcr;
data=io.com_iir;//is bad
if(io.com_iir&UART_IIR_THRE)
io.com_iir &= ~UART_IIR_THRE;
break;
case COM_LCR:
data=io.com_lcr;
break;
case COM_MCR:
data=io.com_mcr;
break;
case COM_LSR:
data=io.com_lsr;
{
#if 0
int ERR_RX,BII,FEI,PEI,OEI;
if(io.com_lsr&UART_LSR_ERR_RX){ ERR_RX=1;io.com_lsr &=~0x80;}
if(io.com_lsr&UART_LSR_BII) { BII=1;io.com_lsr &=~0x10;}
if(io.com_lsr&UART_LSR_FEI) {FEI=1;io.com_lsr &=~0x08;}
if(io.com_lsr&UART_LSR_PEI) {PEI=1;io.com_lsr &=~0x04;}
if(io.com_lsr&UART_LSR_OEI) {OEI=1;io.com_lsr &=~0x02;}
if(ERR_RX|BII|FEI|PEI|OEI) {
io.com_iir=0x0110;
W90P710_set_interrupt(INT_UARTRX0);
W90P710_set_AICISR(INT_UARTRX0);
W90P710_update_int (state);
io.aic_iasr &= ~(1<<9);
}
#endif
}
break;
case COM_MSR:
data=io.com_msr;
break;
case COM_TOR:
data=io.com_tor;
break;
/*Timers Registers */
case TCR0:
data=io.tcr0;
break;
case TCR1:
data=io.tcr1;
break;
case TICR0:
data=io.ticr0;
break;
case TICR1:
data=io.ticr1;
break;
case TDR0:
data=io.tdr0;
break;
case TDR1:
data=io.tdr1;
break;
case WTCR:
data=io.wtcr;
break;
case TISR:
data=io.tisr;
break;
default:
SKYEYE_DBG ("%s (addr = 0x%08x)\n", __FUNCTION__, addr);
break;
}
return data;
}
void
W90P710_io_write_byte (ARMul_State * state, ARMword addr, ARMword data)
{
debug_zswan("W90P710_io_write_byte");
W90P710_io_write_word (state, addr, data);
}
void
W90P710_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data)
{
debug_zswan("W90P710_io_write_halfword");
W90P710_io_write_word (state, addr, data);
}
void
W90P710_io_write_word (ARMul_State * state, ARMword addr, ARMword data)
{
debug_zswan("W90P710_io_write_word");
switch (addr) {
/*System Manager control */
case PDID:
io.pdid=data;
debug_zswan_register(io.pdid,"io.pdid");
break;
case ARBCON:
io.arbcon=data;
debug_zswan_register(io.arbcon,"io.arbcon");
break;
case PLLCON:
io.pllcon=data;
debug_zswan_register(io.pllcon,"io.pllcon");
break;
case CLKSEL:
io.clksel=data;
debug_zswan_register(io.clksel,"io.clksel");
break;
/*Interrupt source Registers */
case AIC_SCR1:
io.aic_scr[0]=data;
debug_zswan_register(io.aic_scr[0],"io.aic_scr[0]");
break;
case AIC_SCR2:
io.aic_scr[1]=data;
debug_zswan_register(io.aic_scr[1],"io.aic_scr[1]");
break;
case AIC_SCR3:
io.aic_scr[2]=data;
debug_zswan_register(io.aic_scr[2],"io.aic_scr[2]");
break;
case AIC_SCR4:
io.aic_scr[3]=data;
debug_zswan_register(io.aic_scr[3],"io.aic_scr[3]");
break;
case AIC_SCR5:
io.aic_scr[4]=data;
debug_zswan_register(io.aic_scr[4],"io.aic_scr[4]");
break;
case AIC_SCR6:
io.aic_scr[5]=data;
debug_zswan_register(io.aic_scr[5],"io.aic_scr[5]");
break;
case AIC_SCR7:
io.aic_scr[6]=data;
debug_zswan_register(io.aic_scr[6],"io.aic_scr[6]");
break;
case AIC_SCR8:
io.aic_scr[7]=data;
debug_zswan_register(io.aic_scr[7],"io.aic_scr[7]");
break;
case AIC_SCR9:
io.aic_scr[8]=data;
debug_zswan_register(io.aic_scr[8],"io.aic_scr[8]");
break;
case AIC_SCR10:
io.aic_scr[9]=data;
debug_zswan_register(io.aic_scr[9],"io.aic_scr[9]");
break;
case AIC_SCR11:
io.aic_scr[10]=data;
debug_zswan_register(io.aic_scr[10],"io.aic_scr[10]");
break;
case AIC_SCR12:
io.aic_scr[11]=data;
debug_zswan_register(io.aic_scr[11],"io.aic_scr[11]");
break;
case AIC_SCR13:
io.aic_scr[12]=data;
debug_zswan_register(io.aic_scr[12],"io.aic_scr[12]");
break;
case AIC_SCR14:
io.aic_scr[13]=data;
debug_zswan_register(io.aic_scr[13],"io.aic_scr[13]");
break;
case AIC_SCR15:
io.aic_scr[14]=data;
debug_zswan_register(io.aic_scr[14],"io.aic_scr[14]");
break;
case AIC_SCR16:
io.aic_scr[15]=data;
debug_zswan_register(io.aic_scr[15],"io.aic_scr[15]");
break;
case AIC_SCR17:
io.aic_scr[16]=data;
debug_zswan_register(io.aic_scr[16],"io.aic_scr[16]");
break;
case AIC_SCR18:
io.aic_scr[17]=data;
debug_zswan_register(io.aic_scr[17],"io.aic_scr[17]");
break;
case AIC_SCR19:
io.aic_scr[18]=data;
debug_zswan_register(io.aic_scr[18],"io.aic_scr[18]");
break;
case AIC_SCR20:
io.aic_scr[19]=data;
debug_zswan_register(io.aic_scr[19],"io.aic_scr[19]");
break;
case AIC_SCR21:
io.aic_scr[20]=data;
debug_zswan_register(io.aic_scr[20],"io.aic_scr[20]");
break;
case AIC_SCR22:
io.aic_scr[21]=data;
debug_zswan_register(io.aic_scr[21],"io.aic_scr[21]");
break;
case AIC_SCR23:
io.aic_scr[22]=data;
debug_zswan_register(io.aic_scr[22],"io.aic_scr[22]");
break;
case AIC_SCR24:
io.aic_scr[23]=data;
debug_zswan_register(io.aic_scr[23],"io.aic_scr[23]");
break;
case AIC_SCR25:
io.aic_scr[24]=data;
debug_zswan_register(io.aic_scr[24],"io.aic_scr[24]");
break;
case AIC_SCR26:
io.aic_scr[25]=data;
debug_zswan_register(io.aic_scr[25],"io.aic_scr[25]");
break;
case AIC_SCR27:
io.aic_scr[26]=data;
debug_zswan_register(io.aic_scr[26],"io.aic_scr[26]");
break;
case AIC_SCR28:
io.aic_scr[27]=data;
debug_zswan_register(io.aic_scr[27],"io.aic_scr[27]");
break;
case AIC_SCR29:
io.aic_scr[28]=data;
debug_zswan_register(io.aic_scr[28],"io.aic_scr[28]");
break;
case AIC_SCR30:
io.aic_scr[29]=data;
debug_zswan_register(io.aic_scr[29],"io.aic_scr[29]");
break;
case AIC_SCR31:
io.aic_scr[30]=data;
debug_zswan_register(io.aic_scr[30],"io.aic_scr[30]");
break;
/*Interrupt Controller Registers */
case AIC_IRSR:
io.aic_irsr=data;
debug_zswan_register(io.aic_scr[31],"io.aic_scr[31]");
break;
case AIC_IASR:
//io.aic_iasr=data;
io.aic_iasr &= (~data);
debug_zswan_register(io.aic_iasr,"io.aic_iasr");
break;
case AIC_ISR:
io.aic_isr=data;
debug_zswan_register(io.aic_isr,"io.aic_isr");
break;
case AIC_IPER:
io.aic_iper=data;
debug_zswan_register(io.aic_iper,"io.aic_iper");
break;
case AIC_ISNR:
io.aic_isnr=data;
debug_zswan_register(io.aic_isnr,"io.aic_isnr");
break;
case AIC_IMR:
io.aic_imr=data;
debug_zswan_register(io.aic_imr,"io.aic_imr");
break;
case AIC_OISR:
io.aic_oisr=data;
debug_zswan_register(io.aic_oisr,"io.aic_oisr");
break;
case AIC_MECR:
io.aic_mecr=data;
debug_zswan_register(io.aic_mecr,"io.aic_mecr");
break;
case AIC_MDCR:
io.aic_mdcr=data;
debug_zswan_register(io.aic_mdcr,"io.aic_mdcr");
break;
case AIC_SSCR:
io.aic_sscr=data;
debug_zswan_register(io.aic_sscr,"io.aic_sscr");
break;
case AIC_EOSCR:
io.aic_eoscr=data;
debug_zswan_register(io.aic_eoscr,"io.aic_eoscr");
io.aic_iper=0x0;//interrupt have finish
break;
case AIC_TEST:
io.aic_test=data;
break;
/*UART Registers */
case COM_TX:
/*Cpu add the data to empty com_tx*/
io.com_tx=data;
io.com_lsr &=~UART_LSR_THRE;//ok
io.com_iir &= ~UART_IIR_THRE;
io.aic_iasr &= ~(1<<9);
debug_zswan_register_key(data,"cpu put the data to COM_TX",1);
{
/*exterior to get the com_tx making the com_tx is empty */
char c = io.com_tx;
//debug_zswan_register_key(data,"COM_TX",1);
write (skyeye_config.uart.fd_out, &c, 1);
//debug_zswan_register_key(&skyeye_config.uart.fd_out,"uart.fd_out",1);
io.com_tx=0x00;
/*because com_tx is empty,so set the interrupt*/
//io.com_lsr |= (UART_LSR_THRE|UART_LSR_TE);
if (io.com_ier!=0x88)
Set_uart_tx_rx_interrupt(0,state);
}
break;
case COM_IER:
io.com_ier=data;
debug_zswan_register_key(data,"io.com_ier",1);
break;
case COM_FCR:
io.com_fcr=0x0f;
io.com_rx=0;
io.com_tx=0;
break;
case COM_LCR:
io.com_lcr=data;
break;
case COM_MCR:
io.com_mcr=data;
break;
case COM_LSR:
io.com_lsr=data;
break;
case COM_MSR:
io.com_msr=data;
break;
case COM_TOR:
io.com_tor=data;
break;
/*Timers Registers */
case TCR0:
io.tcr0=data;
debug_zswan_register(io.ticr0,"io.TCR0");
JUDGE_ENABLE_TIMER(0);
break;
case TCR1:
io.tcr1=data;
JUDGE_ENABLE_TIMER(1);
break;
case TICR0:
if (!ENABLE_TIMER0){
io.ticr0=data;
debug_zswan_register(io.ticr0,"io.ticr0-1");
}
else
{
io.ticr0=0xfff;
debug_zswan_register(io.ticr0,"io.ticr0-2");
}
debug_zswan_register(io.ticr0,"io.ticr0");
break;
case TICR1:
if (!ENABLE_TIMER1){
io.ticr1=data;
debug_zswan_register(io.ticr0,"io.ticr1");
}
else {
io.ticr1=0xfff;
debug_zswan_register(io.ticr1,"io.ticr1");
}
break;
case TDR0:
io.tdr0=data;
break;
case TDR1:
io.tdr1=data;
break;
case WTCR:
io.wtcr=data;
break;
case TISR:
io.aic_iasr &=~(1<<(INT_TIMER0));
break;
default:
SKYEYE_DBG ("%s (addr = 0x%08x)\n", __FUNCTION__, addr);
break;
}
}
void W90P710_io_write_word (ARMul_State * state, ARMword addr, ARMword data); /* W90P710 Internal IO Registers
* */
typedef struct W90P710_io
{
/*********************************/ /*System Manager control */
ARMword pdid;
ARMword arbcon;
ARMword pllcon;
ARMword clksel; /*Interrupt Controller Registers */
ARMword aic_scr[31];
ARMword aic_irsr;
ARMword aic_iasr;
ARMword aic_isr;
ARMword aic_iper;
ARMword aic_isnr;
ARMword aic_imr;
ARMword aic_oisr;
ARMword aic_mecr;
ARMword aic_mdcr;
ARMword aic_sscr;
ARMword aic_sccr;
ARMword aic_eoscr;
ARMword aic_test;
ARMword aic_fiq;
ARMword aic_irq;
/*UART Registers */
ARMword com_tx;
ARMword com_rx;
ARMword com_dll;
ARMword com_dlm;
ARMword com_ier;
ARMword com_iir;
ARMword com_fcr;
ARMword com_lcr;
ARMword com_mcr;
ARMword com_lsr;
ARMword com_msr;
ARMword com_tor; /*Timers Registers */
ARMword tcr0;
ARMword tcr1;
ARMword ticr0;
ARMword ticr1;
int tdr0;
int tdr1;
ARMword tisr;
ARMword wtcr;
/*cache register*/
ARMword cahcnf;
ARMword cahcon;
ARMword cahadr; } W90P710_io_t;
static W90P710_io_t W90P710_io;
#define io W90P710_io
static int ENABLE_TIMER0=0;
static int ENABLE_TIMER1=0;
static unsigned char mac_buf[4096]; int JUDGE_ENABLE_TIMER(int timer)
{
int IE=0,CEN=0,nDBGACK_EN=0;
if(timer==0){
if (io.tcr0&0x20000000) {IE=1;io.aic_isr|=1<<(INT_TIMER0);}
if (io.tcr0&0x40000000) CEN=1;
if (io.tcr0&0x80000000) nDBGACK_EN=1;
if (IE&CEN&nDBGACK_EN) {
io.tdr0=io.ticr0;
return ENABLE_TIMER0=1;
}
}
}
static void
W90P710_update_int (ARMul_State * state)
{
ARMword requests = io.aic_iasr & io.aic_mecr;
/*DEBUG MY FUN*/
debug_zswan_register_key(requests ,"W90P710_update_int-requests & io.aic_irq",0);
/*because i have use the fiq,i delete it*/
state->NirqSig = (requests) ? LOW : HIGH;
//if(requests)
// state->NirqSig =0;
//else
// state->NirqSig =1;
}
static void
W90P710_set_interrupt (unsigned int irq)
{
/*DEBUG MY FUN*/
debug_zswan_register_key(io.aic_iasr,"W90P710_set_interrupt-io.aic_iasr",0);
io.aic_iasr |= (1 << irq);
}
static void
Set_uart_tx_rx_interrupt (int rxtx,ARMul_State * state)
{
int Receiver=1 ,Transmitter=0;
//io.aic_iasr |= (1<<9);
//io.com_iir &= ~0x01;
//Receiver |= ~0x01;
if(rxtx==Receiver){
printf("---Start Receiver interrupt call cpu to get the com_rx---\n");
io.com_iir =UART_IIR_DR;
io.com_lsr |=UART_LSR_RFDR;
}
if(rxtx==Transmitter){
printf("---Start Transmitter interrupt call cpu to put the com_tx---\n");
io.com_iir =UART_IIR_THRE;
io.com_lsr |=UART_LSR_THRE;
}
W90P710_set_interrupt(INT_UARTRX0);
W90P710_set_AICISR(INT_UARTRX0);
W90P710_update_int (state);
io.aic_iasr &= ~(1<<9);
}
void
W90P710_set_AICISR (unsigned int irq)
{
io.aic_iasr |= (1 << irq);
io.aic_mecr |= (1 << irq);
io.aic_isr|=io.aic_iasr&io.aic_mecr;
/*DEBUG MY FUN*/
debug_zswan_register_key(io.aic_iasr,"W90P710_set_AICISR-io.io.aic_isr",0);
}
static int
W90P710_pending_intr (u32 interrupt)
{
return ((io.aic_iasr & (1 << interrupt)));
}
static void
W90P710_update_intr (void *mach)
{
struct machine_config *mc = (struct machine_config *) mach;
ARMul_State *state = (ARMul_State *) mc->state;
W90P710_update_int (state);
}
static void
W90P710_io_reset (ARMul_State * state)
{
/*DEBUG MY FUN*/
debug_zswan_register_key(0,"W90P710 RESET FUNC",0);
/*INIT MY IO REGISTER*/
memset (&W90P710_io, 0, sizeof (W90P710_io));
io.aic_isr = 0x0;
io.aic_mecr=0x0;
io.aic_isr=0x0;
io.aic_iper=0x0;
io.com_iir=0x81818181;
io.com_lsr=0x60606060;
//io.com_ier=0x02|0x01;
}; /*W90P710 io_do_cycle*/
void
W90P710_io_do_cycle (ARMul_State * state)
{
unsigned int t;
fd_set rfds;
struct timeval tv;
int maxfd;
/*Timer */
if (ENABLE_TIMER0) {=====〉1
EBUG MY FUN*/
debug_zswan_register_key(io.tdr0,"io.tdr0--",0);
/*SET INIT DATA*/
io.tdr0--;
if (io.tdr0 < 0) {
/*DEBUG MY FUN*/
debug_zswan_register_key(io.tdr0,"io.tdr0<0",0);
/*RELOAD THE DATA*/
//io.tisr=0x1;
io.tdr0 = io.ticr0;
/*SET UCLINUX INTERRUPPT*/
W90P710_set_interrupt (INT_TIMER0);
/*SET AIC TO UC ENTRY-ARMV.S*/
W90P710_set_AICISR(INT_TIMER0);
W90P710_update_int (state); return;
}
}
/*UART*/
FD_SET (skyeye_config.uart.fd_in, &rfds);
maxfd = skyeye_config.uart.fd_in;
tv.tv_sec = 0;
tv.tv_usec = 0;
if (select (maxfd + 1, &rfds, NULL, NULL, &tv) > 0) {
if (FD_ISSET (skyeye_config.uart.fd_in, &rfds)) {
unsigned char buf;
int n;
n = read (skyeye_config.uart.fd_in, &buf, 1);
if (n > 0) {
if (buf == 1) buf = 3;
io.com_rx = (int) buf;
Set_uart_tx_rx_interrupt(1,state);
//io.aic_iasr &= ~(1<<9);
}
}
}
W90P710_update_int (state);
}
/* IO Read Routine */
ARMword
W90P710_io_read_byte (ARMul_State * state, ARMword addr)
{
debug_zswan("W90P710_io_read_byte");
//printf("SKYEYE: W90P710_io_read_byte error\n");
W90P710_io_read_word (state, addr);
}
ARMword
W90P710_io_read_halfword (ARMul_State * state, ARMword addr)
{
debug_zswan("W90P710_io_read_halfword");
//printf("SKYEYE: W90P710_io_read_halfword error\n");
W90P710_io_read_word (state, addr);
}
ARMword
W90P710_io_read_word (ARMul_State * state, ARMword addr)
{
debug_zswan("W90P710_io_read_word");
ARMword data = -1;
switch (addr) {
/*System Manager control */
case PDID:
data=io.pdid;
break;
case ARBCON:
data=io.arbcon;
break;
case PLLCON:
data=io.pllcon;
break;
case CLKSEL:
data=io.clksel;
break;
/*Interrupt source Registers */
case AIC_SCR1:
data=io.aic_scr[0];
break;
case AIC_SCR2:
data=io.aic_scr[1];
break;
case AIC_SCR3:
data=io.aic_scr[2];
break;
case AIC_SCR4:
data=io.aic_scr[3];
break;
case AIC_SCR5:
data=io.aic_scr[4];
break;
case AIC_SCR6:
data=io.aic_scr[5];
break;
case AIC_SCR7:
data=io.aic_scr[6];
break;
case AIC_SCR8:
data=io.aic_scr[7];
break;
case AIC_SCR9:
data=io.aic_scr[8];
break;
case AIC_SCR10:
data=io.aic_scr[9];
break;
case AIC_SCR11:
data=io.aic_scr[10];
break;
case AIC_SCR12:
data=io.aic_scr[11];
break;
case AIC_SCR13:
data=io.aic_scr[12];
break;
case AIC_SCR14:
data=io.aic_scr[13];
break;
case AIC_SCR15:
data=io.aic_scr[14];
break;
case AIC_SCR16:
data=io.aic_scr[15];
break;
case AIC_SCR17:
data=io.aic_scr[16];
break;
case AIC_SCR18:
data=io.aic_scr[17];
break;
case AIC_SCR19:
data=io.aic_scr[18];
break;
case AIC_SCR20:
data=io.aic_scr[19];
break;
case AIC_SCR21:
data=io.aic_scr[20];
break;
case AIC_SCR22:
data=io.aic_scr[21];
break;
case AIC_SCR23:
data=io.aic_scr[22];
break;
case AIC_SCR24:
data=io.aic_scr[23];
break;
case AIC_SCR25:
data=io.aic_scr[24];
break;
case AIC_SCR26:
data=io.aic_scr[25];
break;
case AIC_SCR27:
data=io.aic_scr[26];
break;
case AIC_SCR28:
data=io.aic_scr[27];
break;
case AIC_SCR29:
data=io.aic_scr[28];
break;
case AIC_SCR30:
data=io.aic_scr[29];
break;
case AIC_SCR31:
data=io.aic_scr[30];
break;
/*Interrupt Controller Registers */
case AIC_IRSR:
data=io.aic_irsr ;
break;
case AIC_IASR:
data=io.aic_iasr ;
break;
case AIC_ISR:
data=io.aic_isr;
debug_zswan_register_key(io.aic_isr,"io.aic_isr",0); break;
case AIC_IPER:
{
int j,k,find[31],max[31];
int max_level,max_irq,l=0;
for(j=0;j<32;j++){
if(((io.aic_iasr) & (1 << j))&((io.aic_mecr & (1 << j)))){
find[l++]=j;
max[l]=io.aic_scr[(find[l--]-1)]&0x07;
l++;
max[l]=7;
continue;
}
}
if(l==0) data=0;
else{
max_level=max[l];
for(j=l;j>0;j--){
if (max[j-1]<=max_level){
max_level=max[j-1];
max_irq=find[j-1];
}
}
}
data=(max_irq<<2);
debug_zswan_register(data,"io.AIC_IPER");
io.aic_isnr=max_irq;
//if(max_level==0) state->NfiqSig =1 ;
//else state->NirqSig =1 ;
}
break;
case AIC_ISNR:
data=io.aic_isnr;
break;
case AIC_IMR:
data=io.aic_imr;
break;
case AIC_OISR:
data=io.aic_oisr;
break;
case AIC_MECR:
data=io.aic_mecr;
break;
case AIC_MDCR:
data=io.aic_mdcr;
break;
case AIC_SSCR:
data=io.aic_sscr;
break;
case AIC_EOSCR:
data=io.aic_eoscr;
break;
case AIC_TEST:
data=io.aic_test;
break;
/*UART Registers */
case COM_RX:
//data=io.com_tx;
data=io.com_rx;
//data=io.com_dll;
io.com_lsr &= ~UART_LSR_RFDR;
io.com_iir &= ~UART_IIR_DR;
io.aic_iasr &= ~(1<<9);
debug_zswan_register_key(io.com_rx,"start to get com_rx",0);
break;
case COM_IER:
//data=io.com_dlm;//ok?
data=io.com_ier;
break;
case COM_IIR:
//data=io.com_fcr;
data=io.com_iir;//is bad
if(io.com_iir&UART_IIR_THRE)
io.com_iir &= ~UART_IIR_THRE;
break;
case COM_LCR:
data=io.com_lcr;
break;
case COM_MCR:
data=io.com_mcr;
break;
case COM_LSR:
data=io.com_lsr;
{
#if 0
int ERR_RX,BII,FEI,PEI,OEI;
if(io.com_lsr&UART_LSR_ERR_RX){ ERR_RX=1;io.com_lsr &=~0x80;}
if(io.com_lsr&UART_LSR_BII) { BII=1;io.com_lsr &=~0x10;}
if(io.com_lsr&UART_LSR_FEI) {FEI=1;io.com_lsr &=~0x08;}
if(io.com_lsr&UART_LSR_PEI) {PEI=1;io.com_lsr &=~0x04;}
if(io.com_lsr&UART_LSR_OEI) {OEI=1;io.com_lsr &=~0x02;}
if(ERR_RX|BII|FEI|PEI|OEI) {
io.com_iir=0x0110;
W90P710_set_interrupt(INT_UARTRX0);
W90P710_set_AICISR(INT_UARTRX0);
W90P710_update_int (state);
io.aic_iasr &= ~(1<<9);
}
#endif
}
break;
case COM_MSR:
data=io.com_msr;
break;
case COM_TOR:
data=io.com_tor;
break;
/*Timers Registers */
case TCR0:
data=io.tcr0;
break;
case TCR1:
data=io.tcr1;
break;
case TICR0:
data=io.ticr0;
break;
case TICR1:
data=io.ticr1;
break;
case TDR0:
data=io.tdr0;
break;
case TDR1:
data=io.tdr1;
break;
case WTCR:
data=io.wtcr;
break;
case TISR:
data=io.tisr;
break;
default:
SKYEYE_DBG ("%s (addr = 0x%08x)\n", __FUNCTION__, addr);
break;
}
return data;
}
void
W90P710_io_write_byte (ARMul_State * state, ARMword addr, ARMword data)
{
debug_zswan("W90P710_io_write_byte");
W90P710_io_write_word (state, addr, data);
}
void
W90P710_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data)
{
debug_zswan("W90P710_io_write_halfword");
W90P710_io_write_word (state, addr, data);
}
void
W90P710_io_write_word (ARMul_State * state, ARMword addr, ARMword data)
{
debug_zswan("W90P710_io_write_word");
switch (addr) {
/*System Manager control */
case PDID:
io.pdid=data;
debug_zswan_register(io.pdid,"io.pdid");
break;
case ARBCON:
io.arbcon=data;
debug_zswan_register(io.arbcon,"io.arbcon");
break;
case PLLCON:
io.pllcon=data;
debug_zswan_register(io.pllcon,"io.pllcon");
break;
case CLKSEL:
io.clksel=data;
debug_zswan_register(io.clksel,"io.clksel");
break;
/*Interrupt source Registers */
case AIC_SCR1:
io.aic_scr[0]=data;
debug_zswan_register(io.aic_scr[0],"io.aic_scr[0]");
break;
case AIC_SCR2:
io.aic_scr[1]=data;
debug_zswan_register(io.aic_scr[1],"io.aic_scr[1]");
break;
case AIC_SCR3:
io.aic_scr[2]=data;
debug_zswan_register(io.aic_scr[2],"io.aic_scr[2]");
break;
case AIC_SCR4:
io.aic_scr[3]=data;
debug_zswan_register(io.aic_scr[3],"io.aic_scr[3]");
break;
case AIC_SCR5:
io.aic_scr[4]=data;
debug_zswan_register(io.aic_scr[4],"io.aic_scr[4]");
break;
case AIC_SCR6:
io.aic_scr[5]=data;
debug_zswan_register(io.aic_scr[5],"io.aic_scr[5]");
break;
case AIC_SCR7:
io.aic_scr[6]=data;
debug_zswan_register(io.aic_scr[6],"io.aic_scr[6]");
break;
case AIC_SCR8:
io.aic_scr[7]=data;
debug_zswan_register(io.aic_scr[7],"io.aic_scr[7]");
break;
case AIC_SCR9:
io.aic_scr[8]=data;
debug_zswan_register(io.aic_scr[8],"io.aic_scr[8]");
break;
case AIC_SCR10:
io.aic_scr[9]=data;
debug_zswan_register(io.aic_scr[9],"io.aic_scr[9]");
break;
case AIC_SCR11:
io.aic_scr[10]=data;
debug_zswan_register(io.aic_scr[10],"io.aic_scr[10]");
break;
case AIC_SCR12:
io.aic_scr[11]=data;
debug_zswan_register(io.aic_scr[11],"io.aic_scr[11]");
break;
case AIC_SCR13:
io.aic_scr[12]=data;
debug_zswan_register(io.aic_scr[12],"io.aic_scr[12]");
break;
case AIC_SCR14:
io.aic_scr[13]=data;
debug_zswan_register(io.aic_scr[13],"io.aic_scr[13]");
break;
case AIC_SCR15:
io.aic_scr[14]=data;
debug_zswan_register(io.aic_scr[14],"io.aic_scr[14]");
break;
case AIC_SCR16:
io.aic_scr[15]=data;
debug_zswan_register(io.aic_scr[15],"io.aic_scr[15]");
break;
case AIC_SCR17:
io.aic_scr[16]=data;
debug_zswan_register(io.aic_scr[16],"io.aic_scr[16]");
break;
case AIC_SCR18:
io.aic_scr[17]=data;
debug_zswan_register(io.aic_scr[17],"io.aic_scr[17]");
break;
case AIC_SCR19:
io.aic_scr[18]=data;
debug_zswan_register(io.aic_scr[18],"io.aic_scr[18]");
break;
case AIC_SCR20:
io.aic_scr[19]=data;
debug_zswan_register(io.aic_scr[19],"io.aic_scr[19]");
break;
case AIC_SCR21:
io.aic_scr[20]=data;
debug_zswan_register(io.aic_scr[20],"io.aic_scr[20]");
break;
case AIC_SCR22:
io.aic_scr[21]=data;
debug_zswan_register(io.aic_scr[21],"io.aic_scr[21]");
break;
case AIC_SCR23:
io.aic_scr[22]=data;
debug_zswan_register(io.aic_scr[22],"io.aic_scr[22]");
break;
case AIC_SCR24:
io.aic_scr[23]=data;
debug_zswan_register(io.aic_scr[23],"io.aic_scr[23]");
break;
case AIC_SCR25:
io.aic_scr[24]=data;
debug_zswan_register(io.aic_scr[24],"io.aic_scr[24]");
break;
case AIC_SCR26:
io.aic_scr[25]=data;
debug_zswan_register(io.aic_scr[25],"io.aic_scr[25]");
break;
case AIC_SCR27:
io.aic_scr[26]=data;
debug_zswan_register(io.aic_scr[26],"io.aic_scr[26]");
break;
case AIC_SCR28:
io.aic_scr[27]=data;
debug_zswan_register(io.aic_scr[27],"io.aic_scr[27]");
break;
case AIC_SCR29:
io.aic_scr[28]=data;
debug_zswan_register(io.aic_scr[28],"io.aic_scr[28]");
break;
case AIC_SCR30:
io.aic_scr[29]=data;
debug_zswan_register(io.aic_scr[29],"io.aic_scr[29]");
break;
case AIC_SCR31:
io.aic_scr[30]=data;
debug_zswan_register(io.aic_scr[30],"io.aic_scr[30]");
break;
/*Interrupt Controller Registers */
case AIC_IRSR:
io.aic_irsr=data;
debug_zswan_register(io.aic_scr[31],"io.aic_scr[31]");
break;
case AIC_IASR:
//io.aic_iasr=data;
io.aic_iasr &= (~data);
debug_zswan_register(io.aic_iasr,"io.aic_iasr");
break;
case AIC_ISR:
io.aic_isr=data;
debug_zswan_register(io.aic_isr,"io.aic_isr");
break;
case AIC_IPER:
io.aic_iper=data;
debug_zswan_register(io.aic_iper,"io.aic_iper");
break;
case AIC_ISNR:
io.aic_isnr=data;
debug_zswan_register(io.aic_isnr,"io.aic_isnr");
break;
case AIC_IMR:
io.aic_imr=data;
debug_zswan_register(io.aic_imr,"io.aic_imr");
break;
case AIC_OISR:
io.aic_oisr=data;
debug_zswan_register(io.aic_oisr,"io.aic_oisr");
break;
case AIC_MECR:
io.aic_mecr=data;
debug_zswan_register(io.aic_mecr,"io.aic_mecr");
break;
case AIC_MDCR:
io.aic_mdcr=data;
debug_zswan_register(io.aic_mdcr,"io.aic_mdcr");
break;
case AIC_SSCR:
io.aic_sscr=data;
debug_zswan_register(io.aic_sscr,"io.aic_sscr");
break;
case AIC_EOSCR:
io.aic_eoscr=data;
debug_zswan_register(io.aic_eoscr,"io.aic_eoscr");
io.aic_iper=0x0;//interrupt have finish
break;
case AIC_TEST:
io.aic_test=data;
break;
/*UART Registers */
case COM_TX:
/*Cpu add the data to empty com_tx*/
io.com_tx=data;
io.com_lsr &=~UART_LSR_THRE;//ok
io.com_iir &= ~UART_IIR_THRE;
io.aic_iasr &= ~(1<<9);
debug_zswan_register_key(data,"cpu put the data to COM_TX",1);
{
/*exterior to get the com_tx making the com_tx is empty */
char c = io.com_tx;
//debug_zswan_register_key(data,"COM_TX",1);
write (skyeye_config.uart.fd_out, &c, 1);
//debug_zswan_register_key(&skyeye_config.uart.fd_out,"uart.fd_out",1);
io.com_tx=0x00;
/*because com_tx is empty,so set the interrupt*/
//io.com_lsr |= (UART_LSR_THRE|UART_LSR_TE);
if (io.com_ier!=0x88)
Set_uart_tx_rx_interrupt(0,state);
}
break;
case COM_IER:
io.com_ier=data;
debug_zswan_register_key(data,"io.com_ier",1);
break;
case COM_FCR:
io.com_fcr=0x0f;
io.com_rx=0;
io.com_tx=0;
break;
case COM_LCR:
io.com_lcr=data;
break;
case COM_MCR:
io.com_mcr=data;
break;
case COM_LSR:
io.com_lsr=data;
break;
case COM_MSR:
io.com_msr=data;
break;
case COM_TOR:
io.com_tor=data;
break;
/*Timers Registers */
case TCR0:
io.tcr0=data;
debug_zswan_register(io.ticr0,"io.TCR0");
JUDGE_ENABLE_TIMER(0);
break;
case TCR1:
io.tcr1=data;
JUDGE_ENABLE_TIMER(1);
break;
case TICR0:
if (!ENABLE_TIMER0){
io.ticr0=data;
debug_zswan_register(io.ticr0,"io.ticr0-1");
}
else
{
io.ticr0=0xfff;
debug_zswan_register(io.ticr0,"io.ticr0-2");
}
debug_zswan_register(io.ticr0,"io.ticr0");
break;
case TICR1:
if (!ENABLE_TIMER1){
io.ticr1=data;
debug_zswan_register(io.ticr0,"io.ticr1");
}
else {
io.ticr1=0xfff;
debug_zswan_register(io.ticr1,"io.ticr1");
}
break;
case TDR0:
io.tdr0=data;
break;
case TDR1:
io.tdr1=data;
break;
case WTCR:
io.wtcr=data;
break;
case TISR:
io.aic_iasr &=~(1<<(INT_TIMER0));
break;
default:
SKYEYE_DBG ("%s (addr = 0x%08x)\n", __FUNCTION__, addr);
break;
}
}
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