Hardware Paging Unit part1

2.4 Paging in Hardware
The  paging  unit translates linear address into physical ones.
Tbe data structures that map linear to physical address are called page tables;they are stored in main
memory and must be properly initialized by the kernel before enabling the paging  unit.

Regular paging
The paging unit of intel processors handles 4KB pages. The 32-bis of alinear address are divided into three fields:
Directory
   the most significant 10 bit
Table
   the intermediate 10 bit
Offset
   the least significant 12 bit
The translation of linear address is accomplished in two steps,each based on a type of translation table.
the first translation table is called Page Directory and the second is called Page Table.

the physical address of the Page Directory in use is stored in the cr3 processor register.The Derectory
field within the linear address determines the entry in the Page Directory that points to the proper Page
Table .the address Table's field,in  turn determines the entry in the  Page Table that contains the physical
address of the frame containing the page.The offset fileds determines the relative position within the page
frame.

The entries of Page Directory and Page Tables have the same structure.Each entry includes the following fileds:

Present flag
   if it is set . the referred page is contained in main memory ;if the flag is 0 the page is not contained
   in main memory and the remaining entry bits may be used by the operating system for its own purposes
Field containing the 20 most significant bits of a page frame physical address
  Since each page frame has  a 4kb capacity its physical address must be a multiple of 4096 so the  12
  least significant bits of the physical address are always equal to 0 .if the field refers to a Page Directory
  .the page  frame contains a Page Table;if it refers to a Page Table,the Page frame contains  a page of data.
Accessed flag
   Is set each time the paging unit address the conrresponding  page frame . this flag may be used by the
   operating  system when selecting pages to be swapped out . the paging unit never resets this flag;
   this must be done by the operating  system
Dirty flag
   Applise only to the Page enties .it is set each time a write  operation is performed on the page frame
   As in  the previous case ,this flag may be used by the operating system when selecting  pages to be swapped
   out.the paging unit  never reset this flag ;this must be done by the operating system .
Read/Write flag
   Contains the access right of the page or of the Page Table
User /Supervisor flag
  contains the privilege level required to access the page or page table.
Two flags called PCD and PWT
  control the way the page or Page Table is handled by the hardwear cache
Page size flag
  Applies only to Page Directory entries if it is set the entry refers to a 4mb long page frame

Hardwear Protection Scheme
 the pageing unit use a different protection scheme form the segmention unit.while intel processors allow
 you possible privilege levels to a segment ,only two privilege levels are associated with pages and Page
 Tables ,because prvileges are controlled by the User/Supervisor flag mentioned up,when this flag is 0 the
 page can be accessed only when the CPL is less  than 3 ,when the flag is 1, the page can always be addressed.
 
 Furthermore ,instead of the three types of access rights associated with segments ,only two type of access
 rights(Read/Write)are associated with pages . if the Read/Write flag of a Page Directory or Page Table entry
 is equals to 0 the correcponding Page Table or page can only be read ; otherwise it can be read and writen.